MODULE Counter

TITLE 'Mike Lhamon'

" BCD Counter Example #1 of a state machine design.

" Nov. 13, 2003    EE481   University of Kentucky

" This example represents the most basic state machine design entry, a table
" Note: The output OUT is high for states (3,4,7) instead of (2,6) !!!!
" Also: Notice in the simulation how the output is formed after the rising
"       edge of the clock, and that the reset works both async and sync.

clock PIN;
reset PIN;

" Output pins
 a, b, c, d, out pin istype 'reg_D';

x macro {.x.} ;        " Macro for dont care
" comment starts with a one, double quote
" not operator  !
" xor operator  $
" xnor operator !$
"  or operator  #
" and operator  &
" addition operator +
" combinational assignment =
" registered assignment    :=

truth_table ( [reset,a, b, c, d, out] :> [a, b, c, d, out]) 
  [1, x,x,x,x,x] :> [0,0,0,0,0];  "Input Sync. reset -> 0
  [0, 0,0,0,0,x] :> [0,0,0,0,0];  "Async reset -> 0
  [0, 0,0,0,0,x] :> [0,0,0,1,0];  "0->1
  [0, 0,0,0,1,x] :> [0,0,1,0,0];  "1
  [0, 0,0,1,0,x] :> [0,0,1,1,1];  "2
  [0, 0,0,1,1,x] :> [0,1,0,0,1];  "3
  [0, 0,1,0,0,x] :> [0,1,0,1,0];  "4
  [0, 0,1,0,1,x] :> [0,1,1,0,0];  "5->6
  [0, 0,1,1,0,x] :> [0,1,1,1,1];  "6
  [0, 0,1,1,1,x] :> [1,0,0,0,0];  "7
  [0, 1,0,0,0,x] :> [1,0,0,1,0];  "8->9
  [0, 1,0,0,1,x] :> [0,0,0,0,0];  "9 ->0
 
" end truth_table;

equations
a.clk = clock;
b.clk = clock;
c.clk = clock;
d.clk = clock;
out.clk = clock;
a.aclr = reset;
b.aclr = reset;
c.aclr = reset;
d.aclr = reset;
out.aclr = reset;

test_vectors
  ( [clock, reset]   -> [a,b,c,d] )
  [x, 1]   -> [x,x,x,x];
  [.c., 1] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 1]   -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [x, 1]   -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [x, 1]   -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
END