MODULE Counter0

TITLE 'Mike Lhamon'

" BCD Counter Example #0 of a state machine design.
" Nov. 13, 2003     EE481   University of Kentucky

" This example represents direct entry of a state machine design entry.
" This design counts from 0-9 with OUT high for states 3,4,7
"
" Note: The output OUT is high for states (3,4,7) instead of (2,6) !!!!
" Also: Notice in the simulation how the output is formed after the rising
"       edge of the clock, and that the reset works both async and sync.

clock PIN 1;   " Pin assignments are optional
reset PIN 2;   " Assigning pins reduces re-wiring but contricts to optimizer

" Output pins
 a, b, c, d, out pin 14,15,16,17, 18 istype 'reg_D' ;

x macro {.x.} ;        " Macro for dont care
" c macro {.c.} ;        Macro for clock signal in simulation
" comment starts with a double quote
" not operator  !     
" xnor operator !$                 xor operator  $
"  or operator  #                  and operator  &
" addition operator +
" combinational assignment =       registered assignment  :=

equations
a.clk = clock;   " Although the clock to the D-FF of a 22v10 is fixed, the compiler 
b.clk = clock;   "     doesnt know this.  It is the job of the fitter to match resources.
c.clk = clock; 
d.clk = clock;
out.clk = clock;
a.aclr = reset;
b.aclr = reset;
c.aclr = reset;
d.aclr = reset;
out.aclr = reset;

" Design came from pincel and paper work and k-maps
" The reset input was not part of the original PS/NS table and k-maps and was
"      added late a kludge.
a := !reset & (!a & b & c & d  #  a & !b & !c &!d);
b := !reset & (!a & b &!c  #  !a & b & !d  #  !a & !b & c & d);
c := !reset & (!a & !c & d  #  !a & c & !d);
d := !reset & (!a & !d  #  !b & !c & !d);
out := !reset & ( !a & !b & c & !d  #  !a & !b & c & d  #  !a & b &c & !d);


test_vectors
  ( [clock, reset]   -> [a,b,c,d] )
  [ x , 1] -> [0,0,0,0];
  [.c., 1] -> [0,0,0,0];
  [.c., 0] -> [0,0,0,1];
  [.c., 0] -> [0,0,1,0];
  [.c., 1] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [ x , 1] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [ x,  1] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];
  [.c., 0] -> [x,x,x,x];

END