EE481 Logical Design Lab
Fall 2003, Lab #3

Prelab Questions

1. Design a 1/2 adder using only NAND gates.
2. Show a design of a full adder with a minimum number of gate delays (any gates you want). In addition, show the same design using only 3 input NAND gates.
3. Work out the following arithmetic and show whether overflow occurs.(R and DR stand for Radix and Diminished radix forms). Diminished Radix (DR) is 1's complement, and Radix (R) is 2's complement.
   1. DR(01010) + DR(11001)
   2. R(01010) + R(11001)
   3. DR(11001) - DR(01011)
   4. DR(01010) - R(11001)
4. Show the block diagram of a 8 bit Radix Adder-Subtractor using only Full Adders and XORs.
5. Design a 3-bit carry look ahead adder that includes overflow detection (use XOR's to minimize gate delays).
   Questions pertaining to BCD code
   
6. Show a design for a BCD adder with carry-in and carry-out lines.
7. Convert:
   1. 843(base 10) to it's 8421 BCD equivalent
   2. 51(base 10) to it's 8421 BCD equivalent
   3. 1001 0111 (8421 BCD) to it's decimal equivalent

Experiments

1. Design and implement a 2's complement adder/subtractor using a 74283 chip and a 7486 chip.
2. Implement a 2-bit 2's compliment (radix) ripple carry adder/subtractor that includes overflow detection (use XORs when possible, e.g., in your 1/2 adders).
3. Experimentally compare the propagation delay of the two 2-bit adders you built with the theoretical delay expected?