ECE 4170: Introduction to HDL Based Design

2007 Spring Semester

Prerequisite: ECE 2031

Course Objective: Introduction to hardware description languages and associated methodologies for digital system design. In depth coverage includes applications to the simulation and synthesis of digital systems. Detailed coverage of VHDL and modern standards employed with HDLs for system-on-chip design. An introduction to competing HDL languages. The course has a significant project component to re-enforce language concepts in the context of modern systems-on-chip.

Recommended Text:  VHDL: From Simulation to Synthesis, S. Yalamanchili, Prentice Hall (pubs.). Alternative sources of information, class notes, and supplemental readings will be assigned.

Course Syllabus: http://www.ece.gatech.edu/academics/courses/course_outline.php?prmCourse=ECE4170

Instructor:	Sudhakar Yalamanchili	Teaching Assistant: Contact Information: Office Hours:	Michael Bales Email: mbales3@mail.gatech.edu TTH 12-1:30, Klaus 1448 (The SUN Laboratory)
Contact Information:	Klaus Advanced Computing Building (KACB) 2316 Tel: 404-894-2940 Email: sudha@ece.gatech.edu
Office Hours:	MW 12:30 PM – 2:30 PM
Class:	MW 11:05 PM – 11:55 PM , Van Leer (VL) C340
Grading:	Exam I – 20%, Exam II – 20% Final/Project – 40% Assignments – 20%
Exam Schedule:	Exam I – February 20^th, 7:30pm – February 21^st, 7:30pm. Exam I Solutions Exam II, Due: Thursday, March 29^th, noon
Assignment Schedule:	Assignment 1 : Due February 7^th, 9pm. Assignment 2: Due February 14^th, 9pm. Proposal: Due February 7^th, 2007, 9pm. Assignment 3: Due February 20^th, 9pm. Assignment 4: Due March 16^th, 9pm (check below for links to standards) Requirements and Test Document: Due February 28^th, 9pm. Functional Design Document: Due April 11^th, 9pm. Project Aids: OpenRISC Infrastructure (Note: This is a 24MB file!) Xilinx Synthesis Tutorial Intermediate Project Submission: Due April 17^th, 9 pm. Final Project Submission: Due April 27^th, 9pm. Final Exam : Due 5:40 pm, May 1^st, 2007
Laboratory Information	TBA
Attendance: Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams are not guaranteed to be the same as the exam given in class. Academic Honesty: Although students are encouraged strongly to work together to learn the course material, all students are expected to complete quizzes and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

Schedule of Lectures & Class Resources

Module #	Topic	Notes
1	Introduction and Course Overview
2	Modeling Digital Systems Simulation vs. Synthesis
3	VHDL Basic Language Concepts: Simulation VHDL Basic Language Concepts: Delay Models
4	Modeling Complex Behaviors	Assignment 1: Due February 7^th, 9 pm
5	Input Output & Testbenches	Some Helpful Example Exercises: Example1 : Zip File
6	Structural Models	Proposal Format: Due February 7^th, 9pm
7	Programming Mechanics	Helpful Examples: Example 2
8	Subprograms, Packages, and Libraries	Assignment 2: Due February 14^th, 9pm. Requirements and Test Document: Due February 28^th, 9pm.
9	Basic Language Constructs: Synthesis	Assignment 3: Due February 20^th, 9pm
		Exam I – February 20^th, 7:30pm – February 21^st, 7:30pm Exam I Solutions
10	Modeling Complex Behaviors: Synthesis	HDL Coding Styles: Xilinx RASSP VHDL Coding Styles Introduction to The Open Core Protocol The RTL Subset: IEEE 1076.6 Standard Synthesis Support: IEEE 1076.3 Standard
11	The Open Core Protocol	www.ocp-ip.org OCP 2.1 Standard
12	Summary of Verilog (Due to Prof: G. DeMicheli)	A Nice Short Verilog Tutorial from Bucknell Xilinx Synthesis Tutorial
	Spirit Consortium	http://www.spiritconsortium.org/home
13	VHDL: Advanced Topics	Exam II: Due Thursday noon, March 29^th.
	Summary and Wrap up	OpenRISC Infrastructure (Note this is a 24MB file) Final Project Reports Due: April 27^th, 9pm.
	Final Examination May 1^st, (2:50 – 5:40)

Questions and comments to Sudhakar Yalamanchili
last revised on May 1, 2007