![](../../IMAGES/L1.GIF) | Advantages of using VHDL | ![](../../IMAGES/L2.GIF) |
- VHDL offers several advantages to the system level designer
- Standard language
- Fully expressive language
- Hierarchical
- Configurable
- Tool availability
- Consistency and completeness checks automatic
- Tight coupling to lower levels of design
- Supports hybrid modeling