 | System Level VHDL Constructs-- Notes Page -- | 
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| System Level VHDL Constructs-- Notes Page -- |
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The ATT_MVL logic library supports high-level system modeling in VHDL
and will be the source of some of the syntax examples in the next few
slides. This logic package has multiple logic values and various
functions defined to convert the ATT package to integers. Also,
various operators are overloaded to handle the ATT package.
[Bhasker95]