The add procedure is shown here as a representative of the set of procedures
necessary to implement the behavior of each op code.
Data is represented in 2's-complement form. Thus, most of the VHDL code is
used to check for various boundary conditions resulting from the operation.
In this procedure, the first section of the IF-THEN-ELSE statement checks
for postive overflow, the second for negative overflow and the last
performs addition without overflow of either kind.
If there is positive overflow then it requires that OP2 be greater than
zero and OP1 be greater than the difference between the highest possible
integer represented with 32 bits and OP2. This is the only possible
instance where positive overflow can occur. If positive overflow does
occur, then the result must adjusted to reflect its final representation
in 2's complement form. This modification is shown as the first argument
to the int_to_bits routine and is left as an exercise for the user to
verify its correctness. In this case the V bit is set to '1' to notify the
user that overflow has occurred.
If there is negative overflow then it requires that OP2 be less than
zero and OP1 be less than the difference between the lowest possible
integer represented with 32 bits and OP2. It again is an exercise for
the user to verify the correctness of the first argument to the
int_to_bits routine. In this case the V bit is set to '1' to notify the
user that overflow has occurred..
If no overflow will result from the sum, the operands are added and the
overflow bit, V, is set to '0'. Finally, the N and Z bits are
appropriately set and the procedure exits.
