 | Testbench Body-- Notes Page -- | 
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| Testbench Body-- Notes Page -- |
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The body of the testbench is simply the instantiation of the three system components. It should be noted that there is no mechanism defined for generating test vectors or reading them from a file. To simulate the SDSP, the user must first write the SDSP object code instructions into simulated memory using the VHDL simulator support system, and then start the simulation.