Here, we see an example of behavioral VHDL which includes the use of
VHDL signals as well as variables. A process is shown which includes
a series of statements executed sequentially. The process itself,
however, is executed concurrently with the assignments to A and
Z. The ability to model both concurrent and sequential events
in a VHDL model will be covered in detail in subsequent sections of
this module.
Note that variables are also shown; these are unique to behavioral
VHDL in that they can only be used inside processes. It is important
to point out that this material will not cover shared or global
variables added in the VHDL 93 revisions.
The functionality of the component is defined in the architecture
body. Two signals, A and B are defined internal to the
component. Three statements are defined:
A(0) <= X AFTER 20 ns;
A(1) <= Y AFTER 40 ns;
PROCESS (A);
The process executes the Fourier transform of A using a
function and transfers the results to signal B. All three
statements execute concurrently. The two signal assignment statements
are activated whenever a signal in their respective right-hand sides
changes value. The process becomes active when there is a change in
A.
