VHDL Objects
Scoping Rules
VHDL limits the visibility of the objects, depending on where they are declared
The scope of the object is as follows
Objects
declared in a package are global to all entities that use that
package
Objects declared in an entity are global to all architectures that use that
entity
Objects declared in an architecture are available to all statements in that
architecture
Objects declared in a process are available to only that
process
Scoping rules apply to
constants
,
variables
,
signals
and
files
