Sample VHDL Design Process

Note that the code used in the example is "pseudo code" and not intended to follow VHDL syntax.

The requirement is to design a single bit adder with carry and enable functions. The inputs x, y, and enable are single bits with enable active high. The output of result is the bit addition of x and y and the carry output is the carry generated by the addition. When the enable line is low, the adder is to output zeroes.

This sample design sequence is directly based on an example in [Navabi93].