Exercises 2.
Q1. a) Design a 3 bit pipelined Carry Propagate Adder (CPA).
b) Give a snapshot of all registers, inputs and outputs for input data Ati & Bti
[i=2,1,0..... t=5,4,3,2,1 0 clock cycles].
Q2. a) Design a 4 bit Carry Look Ahead Adder (CLA) assume
all gates have a delay of t=1ns XORgate t=1.5ns Determine maximum frequency of
operation b) Design a 4 bit CPA using two bits CLA Compare your results to above
(a) in term of area & speed. assume 2 input gates =
1gate
3 input=
1.5 gate, 4 input = 2
gates, 5 input
gate =
2.5, 2 input XOR = 2 gates.
Q3. Design a serial adder accumulator for 4 bit long number operands, using 2 reg
isters 6 bits long, one full adder and a FF.
a) Give snapshot for 5 Cycles
b) Determine Latency
c) Determine throughput
d) Determine the maximum number of operands that can be accumulated.
**** In all questions assume FF & registers have zero delay. Assume,
t sum= 1ns, tcry=1.5ns.