Defining the SUM and CARRY functions of a full-bit adder
as logic gate circuits can be represented in VHDL as a single
sequential assignment statement:
SUM <= A xor B xor Cin;
CARRY <= A and B
or A and Cin
or B and Cin;
We can represent these two functions in separate process statements
(but both in the same architecture, as shown here), or together in the
same process statement.
In the example shown, the sensitivity lists are composed of all
signals on the right-hand side of the signal assignment statements.
We really don't need the explicit sensitivity lists since the default
in VHDL is to be sensitive to all right-hand signals. But it doesn't
hurt to show them explicitly. In fact, it makes the process easier to
understand.
