After the component is declared, it must be instantiated. The
and_gate from the previous page is declared and instantiated in a
design on this slide. The instantiation statement must specify at
least three pieces of information to the architecture. First, the
component must be named. Next, the type of the component instantiated
must be specified. Finally, the mapping of the interface to other
signals or ports is completed with the PORT MAP construct.
If the component contained generics, then a generic map could also be
contained in the instantiation. The instantiation statement can be
read as follows. The component named Gate1 is of component type
and_gate which is declared in the architecture declaration
region of architecture test. The signals on its ports are tied
as follows, input in1 is tied to the circuit board signal
S1, input in2 is tied to S2, and the output
out1 is tied to circuit board signal S3.
In this example, each signal is explicitly associated to a port on the
component. The use of the arrows makes the association completely
clear. VHDL also allows for positional association which will be shown
in subsequent slide.
