The following architecture is a second and more robust attempt
The use of 'LAST_VALUE ensures the clock is rising from a 0 value
ARCHITECTURE behavior OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable ='1') AND a'STABLE(x_setup) AND
(clk = '1') AND (clk'LASTVALUE = '0') THEN
b <= a AFTER prop_delay;
END IF;
END PROCESS;
END behavior;
Elaboration of the IF-THEN-ELSE structure could define the behavior under all conditions
