The SDSL Benchmark set of slides show a SDSP program, a random number
generator, in part to illustrate how to embed timing marks in the
benchmark routine such that the VHDL model will report cycle times
automatically.
The first thing done in the program is to set R0 to zero followed by a
branch to the beginning of the program. starttrigger and
donetrigger are used to notify the SDSP model when the random
number generator program is beginning and ending. Our purpose here is
to count the total number of clock cycles used by the benchmark
program, excluding for the R0 initialization.
A few VHDL statements need to be added to the SDSP memory model to
look for specific addresses on the bus. When the starttrigger
address is seen, a counter is started which increments each clock
cycle. When the stoptrigger address is seen, the contents of
the counter are multiplied by the clock cycle time and reported via an
assert or textio write statement.
