Memory is modeled as an array of 32-bit numbers. The length of the
memory is defined as a constant here, but could be made a generic for
more modeling flexibility.
As in the processor model, the input-to-output delay of the memory is
modeled by Tpd. By defining Tpd as a generic, one can
evaluate SDSP performance where the processor and memory differ in
execution speeds.
The memory is usually disconnected from d_bus with ready
deasserted while it waits for a read or write command. Upon receiving
a read or write, memory is then read or written.
