The PORT declaration describes the interface of the entity to
all other VHDL entities. There are three essential elements to
the PORT declaration: the name, mode, and type of the signals in the
interface. A fourth element (not shown above) in a port declaration
is the optional initial value which may be assigned to each signal if
there are no active drivers on the signal at the start of a simulation.
Note that signals declared in an entity's PORT declaration may
sometimes be referred to as ports.
