The next few slides show the behavioral model for the SDSP. The
entity description only provides a description of the ports and the
single generic, Tpd, which is the delay time in the processor
between input events and output signal changes.
The address bus can be modeled as a simple bit vector, but the data
bus must be defined as a resolved bit vector since it can be driven
either by the processor or the memory. The bus indication for
d_bus in the port declaration means that all bits of
d_bus can be disconnected at the same time. Note that aliases
are used to provide meaningful names for the fields of the instruction.
The next few slides will show the memory read and write
procedures, a representative data-path procedure, add, and
finally the main routine in the model which executes the
fetch-decode-execute cycle of the SDSP.
