In this slide the term entity refers to the VHDL construct in
which a component's interface (which is visible to other components)
is described. The first line in an entity declaration provides
the name of the entity.
Next, the PORT statement indicates the actual interface of the
entity. The port statement lists the signals in the
component's interface, the direction of data flow for each
signal listed, and type of each signal. In the
above example, signals x, y, and enable are of
direction IN (i.e. inputs to this component) and type bit, and
carry and result are outputs also of type bit.
Notice that if signals are of the same mode and
type, they may be listed on the same line.
Particular attention should be paid to the syntax in that no semicolon
is required before the closing parenthesis in the PORT declaration (or
GENERIC declaration, for that matter, which is not shown here). The
entity declaration statement is closed with the END keyword, and the
name of the entity is optionally repeated.
