SDSP Bus Write Timing
-- Notes Page --
Memory Write:
During a Ti state, the CPU places an address on
A_BUS
. T1 is the next state
After the leading edge of
phi1
, the CPU asserts
write
to initiate a write activity in the memory. Data to be written is placed on
D_BUS
.
T2 states occur until
ready
is asserted by the memory
Memory deasserts
ready
on falling edge of
write
and removes address and data from
A_BUS
and
D_BUS
respectively
