The signals shown in the entity are all single-bit except for the
address bus, A_BUS, and the data bus, D_BUS, which are
32-bits each.
The clock is a two-phase clock with non-overlapping phases. Each
cycle of phi1 defines a bus state of which there are three: Ti,
T1 and T2. Ti is the idle state.
A bus transaction (e.g., read or write memory) consists of a T1 state
followed by one or more T2 states. The fetch port is a status
signal indicating an instruction fetch is in progress. The
ready port is set by the memory to indicate that read data is
available or write data has been accepted.
