The SDSP processor is a full 32-bit system (both data and
instructions). It is organized along the lines of a RISC architecture.
For example, every instruction is exactly 32-bits in length (plus
32-bit displacement if needed).
To keep the SDSP simple there are a few capabilities missing. For
example, the SDSP has no interrupt capability, nor does it have
subroutine support. But due to the nature of the model, these items
can be very easily and quickly added. The three condition code
register bits are updated after each arithmetic or logical instruction.
- Z - zero bit
- set if the result is zero
- N - negative bit
-
set if the result of an arithmetic instruction
is negative
- V - overflow bit
-
set if a carry or borrow is created from MSB or
LSB, respectively
The PC is set to zero on reset, and the values in the other registers
are not specified. By convention, R0 is read-only and always contains
zero (not enforced by hardware). The PC is incremented to point to the
next address after each instruction is fetched.
