To review, note that some delay must transpire after a VHDL signal
assignment statement before the signal assumes its new value. Examples
will be used in this and the next slide to illustrate the
difference between signals and variables. The example shown above
utilizes signals.
The table indicates the values for the various signals at the key
times in the example. At time 1, a new value of 1 is observed on
a. This causes the out_1 assignment statement to be
evaluated resulting in a 0 being assigned to out_1. At time
1+d (i.e. 1 plus 1 delta cycle), out_1 assumes its new value
causing the out_2 assignment statement to be evaluated
resulting in a 1 being assigned to out_2. At time 1+2d,
out_2 assumes its new value of 1. This example, then, requires
2 delta cycles to arrive at its quiescent state following a change to
a (or b, for that matter)
Note that the two signal assignment statements above are
actually concurrent signal assignment statements so that the
order in which they appear in the model is not important. In each
case, it is a change (or more accurately, a transaction) in one
of the signals in the "right hand side" that results in a
concurrent signal assignment statement being evaluated.
