 | Potential Problems to Avoid-- Notes Page -- | 
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| Potential Problems to Avoid-- Notes Page -- |
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Interestingly, even thought VHDL is considered to be strongly typed,
the developers of the language decided to strongly type only with
respect to the base type, not derived subtypes.
Thus, the VHDL analyzer will not be aware of inconsistent subtypes in
the example shown here, and the simulator will execute the statements
as expected. Note, however, that the result after multiplying
A and B may be out of the range of B's subtype.