The enumerated data type allows a user to specify the list of
legal values that a variable or signal of the defined type may be
assigned. As an example, this data type is useful for defining the
various states of a FSM with descriptive names.
The designer first declares the members of the enumerated type. In
the example above, the designer declares a new type binary with
two legal values, ON and OFF.
Note that VHDL is not case sensitive. Typing reserved words in
capitals and variables in lower case may enhance readability, however.
