The example shown here provides a similar functionality to the TEXTIO
example shown previously. The ASSERT statements are used to display
the current state of an FSM. Note that these ASSERT statements are
concurrent. ASSERTs can be concurrent or sequential depending on
whether they appear inside or outside VHDL processes. In fact,
because they are passive statements (i.e. no assignments are made)
ASSERT statements can also be put in VHDL ENTITY statements.
In the example here, if the "good" state is defined to be 1, then the
first ASSERT will trigger when current_state is not equal to 0. The
second ASSERT statement is set up in a similar fashion.
While this mechanism is similar to the previous TEXTIO example, it can
provide more information to the user and the simulator. The SEVERITY
level may cause the simulator to pause or stop altogether. While
these definitions are implementation defined, they can be useful.
