VHDL defines two different schemes for the GENERATE statement. These
are the FOR-scheme and the IF-scheme. This slide shows the syntax for
the FOR-scheme.
The FOR-scheme works in a similar manner as the FOR loop. The
FOR-scheme generates the objects for a certain number of times and
stops. In the FOR-scheme, all the objects are the same. The loop
variable can be created in the GENERATE statement but it is undefined
outside that statement.
The syntax for the FOR-scheme GENERATE statement is shown in the
slide. The loop variable in this case is N, but can be any valid VHDL
identifier. The range can be any valid range, but must be discrete.
After the GENERATE statement, the concurrent statements to be
generated are stated. Finally, the GENERATE statement is closed by the
END GENERATE construct.
