Wait statements are used to suspend the execution of a process until
some condition is satisfied. Processes in VHDL are actually code
loops. The execution of the last statement in the process is followed
by the execution of the first statement in the process, and process
execution continues until a wait statement is reached. For this
reason, every process must have at least one wait statement (a
sensitivity is actually an implied wait statement which will be
described in the next page of this module).
The structure of a wait statement contains optional clauses which can
be used in any combination:
- The sensitivity_clause:
- the wait statement will only evaluate its
condition clause when there is an event (i.e. a change in value) on
at least one of the signals listed in the sensitivity_clause. If no
sensitivity_clause is given, the signals listed in the
condition_clause constitute an implied sensitivity_clause.
- The condition_clause:
- an expression which must evaluate to TRUE in
order for the process to proceed past the wait statement. If no
condition_clause is given, a TRUE value is implied when there is
an event on a signal in the sensitivity_clause.
- The timeout_clause:
- specifies the maximum amount of time the
process will remain suspended at this wait statement. If no
timeout_clause is given, STD.STANDARD.TIME'HIGH-STD.STANDARD.NOW
(effectively until the end of simulation time) is assumed.
Wait statements assist the modeling process by synchronizing
concurrently executing processes, implementing delay conditions into a
behavioral model, or establishing event communications between
processes. Sometimes, wait statements are used to sequence process
execution relative to the simulation cycle.
