Component instantiation must follow some rules to make sure the
interface of the component and other objects match. To make
discussion of this topic easier, the ports on the component are known
as locals. Each local must match with an
actual. An actual is a signal or formal port declared
in the entity statement. As the picture above indicates, variables and
constants cannot be associated with a port on a component; signals are
the primary means of communication between VHDL entities and
components.
