Sequential statements are used within processes and are executed in a
top-down fashion. The list shown on this page includes many of the
commonly used forms, but the list is not complete. The VHDL Language
Reference Manual (IEEE Std. 1076-1993) provides a complete list.
Each of these statement types will be explained in further sections of
this module. Some of you may note that these control structures
operate almost exactly like their counterparts in Ada except for the
assert and sequential signal assignment statements.
