Technical Questions

1. How to model large amount of memory without using too much simulation memory space?
2. How to model Transport and Inertial Delays in Verilog?
3. How to display the system date in $display or $write?
4. How to display bold characters?
5. How to compile Verilog files from Emacs?

The Verilog-XL release directory comes with a PLI example called "damem". I believe other vendors also provide it as a PLI example. It was never copyrighted.

Here are some excerpts from the appnote.

System tasks:
 $damem_declare
 $damem_read
 $damem_write
 $damem_initb
 $damem_inith
=============================
The $damem_declare System Task
=============================
The $damem_declare system task declares a memory in your design. It is an alternative to the use of the reg keyword to declare an array of regs. When you use the $damem_declare system task to declare a memory in a design, Verilog-XL does not allocate memory space in your workstation for that memory in your design until you enter another system task for dynamically allocated memories ($damem_write,
$damem_initb, or $damem_inith) that writes data to that memory in your design. When Verilog-XL allocates this memory space, it only allocates enough memory space to hold the data written to that memory in your design.

$damem_declare(name_of_memory,bit_from,bit_to, addr_from, addr_to);
$damem_write (name_of_memory,addr,value);
$damem_read(name_of_memory,addr,register);

module delay(in,transport,inertial);
   input in;
   output transport;
   output inertial;

   reg   transport;
   wire   inertial;

   // behaviour of delays
   always @(in)
     begin
        transport <= #10 in;
     end

   assign #10 inertial = in;

endmodule // delay

The timing Diagram for input and outputs
                 _______     __
in         _____|     |_____||_______

                    _______     __
transport  _________|     |_____||_____

                    _______
inertial   _________|     |____________

Non blocking assignment gives you transport delay. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified "transport" delay.

In Continuous assign statement the latest event overrides the earlier event in the queue.

I am attaching rudimentary testbench and its output. Hope this helps.

module test;
   reg  in;
   wire transport, inertial;

   // instantiate delay module
   delay my_delay(in,transport,inertial);

   // apply inputs
   initial
     begin
        in = 0;
        #20 in = 1;
        #20 in = 0;
        #30 in = 1;
        #5  in = 0;
        #30 in = 1;
        #30 $finish;
     end
   // monitor signals
   initial
     begin
        $monitor($time,"  in = %b  transport = %b inertial = %b",
                 in,transport, inertial);
     end

endmodule // test

log file
Compiling source file "delay.v"
Highest level modules:
test

                   0  in = 0  transport = x inertial = x
                  10  in = 0  transport = 0 inertial = 0
                  20  in = 1  transport = 0 inertial = 0
                  30  in = 1  transport = 1 inertial = 1
                  40  in = 0  transport = 1 inertial = 1
                  50  in = 0  transport = 0 inertial = 0
                  70  in = 1  transport = 0 inertial = 0
                  75  in = 0  transport = 0 inertial = 0
                  80  in = 0  transport = 1 inertial = 0
                  85  in = 0  transport = 0 inertial = 0
                 105  in = 1  transport = 0 inertial = 0
                 115  in = 1  transport = 1 inertial = 1
L35 "delay.v": $finish at simulation time 135
81 simulation events

$system is not an IEEE Standard(1364-1995), but is supported by both XL and VCS.

You could read back in the output of $system, by writing it to another file and reading it back in using $readmemh() as illustrated in following example.

module top;

reg [23:0] today [0:1];

initial
begin
    $system("date +%m%d%y  > date_file");
               // output is 073199 for july 31st 1999
    $readmemh("date_file", today);
    $display("Today is: %x", today[0]);
end
endmodule

module bold;

 initial begin

   $display ("Normal Text");
   $display ("\033[1mBold Text");
   $display ("\033[mSwitch back to Normal Text.....");
   $display ("\033[7mInverse Text.");
   $display ("\033[mSwitch back to Normal Text.....");

   $display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text \033[m");
 end

endmodule

How to compile Verilog files from Emacs?

Contributed by Petter Gustad

You can make Emacs start your simulator by putting this in .emacs (assuming you're using
verilog-mode):

(add-hook 'verilog-mode-hook
(lambda ()
(make-local-variable 'compile-command)
(setq compile-command "./trun --vcs +SST")))

Then I have
(global-set-key [f9] 'compile)

Whenever I hit F9 it will run the compile command. If I'm working on C
code that will be make. If I'm using verilog mode that will be "./trun --vcs +SST", e.g. a script to run my testbench and generate a signalscan dump file.