\part{F-CPU Instruction Set draft}

\input html2latex

\setcounter{chapter}{0}

\chapter{Arithmetic Operations}

\section{Core Arithmetic operations}

\input i7/Draft/Integer/add
\input i7/Draft/Integer/sub
\input i7/Draft/Integer/mul
\input i7/Draft/Integer/div

\section{Optional Arithmetic operations}

\input i7/Draft/Integer/addi
\input i7/Draft/Integer/subi
\input i7/Draft/Integer/muli
\input i7/Draft/Integer/divi
\input i7/Draft/Integer/rem
\input i7/Draft/Integer/remi
\input i7/Draft/Integer/mac
\input i7/Draft/Integer/addsub
\input i7/Draft/Bits/popcount
\input i7/Draft/Bits/popcounti

\section{Optional increment-based operations}

~~~~~~
These instructions are only performed when the Increment Unit is implemented,
which is optional but recommanded when performance is critical in the FC0 for
example. The INC unit has recently been extended to support signed operations, 
so the instructions can be used on signed numbers as well as floating point 
numbers.

\input i7/Draft/Integer/inc
\input i7/Draft/Integer/dec
\input i7/Draft/Integer/neg

\input i7/Draft/Bits/scan

\input i7/Draft/Integer/cmpl
\input i7/Draft/Integer/cmple
\input i7/Draft/Integer/cmpli
\input i7/Draft/Integer/cmplei

\input i7/Draft/Integer/abs
\input i7/Draft/Integer/max
\input i7/Draft/Integer/min
\input i7/Draft/Integer/maxi
\input i7/Draft/Integer/mini
\input i7/Draft/Integer/sort


\section{Optional Logarithmic Number System operations}

~~~~~~
These opcodes are reserved for an eventual support of the Logarithmic Number
System ({\it LNS}) in F-CPU versions that are too small to support Floating 
Point operations. Note that the LNS numbers can currently not exceed 32 bits 
but this can change in the future. The bit \#11 that is reserved in most 
integer instructions can be used to specify that the data is in the LNS or 
fractional format but this is not yet decided.

\input i7/Draft/LNS/ladd
\input i7/Draft/LNS/lsub
\input i7/Draft/LNS/l2int
\input i7/Draft/LNS/int2l



\chapter{Bit Shuffling based operations}


\section{Core Shift and Rotate operations}

\input i7/Draft/Bits/shiftl
\input i7/Draft/Bits/shiftr
\input i7/Draft/Bits/shiftra
\input i7/Draft/Bits/rotl
\input i7/Draft/Bits/rotr


\section{Optional Shift and Rotate operations}

\input i7/Draft/Bits/shiftli
\input i7/Draft/Bits/shiftri
\input i7/Draft/Bits/shiftrai
\input i7/Draft/Bits/rotli
\input i7/Draft/Bits/rotri
\input i7/Draft/Bits/bitop
\input i7/Draft/Bits/bitopi


\section{Optional Bit Shuffling operations}

~~~~~~
The Bit Shuffling Unit of the F-CPU can also perform other operations than
simply rotating or shifting bits. Its purpose is to change the position of 
the bits, which also includes bit and byte reversing and SIMD packing 
operations.

\input i7/Draft/Bits/bitrev
\input i7/Draft/Bits/bitrevi
\input i7/Draft/Bits/byterev

\input i7/Draft/Bits/dbitrev
\input i7/Draft/Bits/dbitrevi
\input i7/Draft/Bits/dshiftl
\input i7/Draft/Bits/dshiftli
\input i7/Draft/Bits/dshiftr
\input i7/Draft/Bits/dshiftri
\input i7/Draft/Bits/dshiftra
\input i7/Draft/Bits/dshiftrai

\input i7/Draft/Bits/mix
\input i7/Draft/Bits/expand
\input i7/Draft/Bits/sdup



\chapter{Logic operations}


\section{Core Logic operations}

\input i7/Draft/Bits/logic


\section{Optional Logic operations}

\input i7/Draft/Bits/logici



\chapter{Floating Point Operations}

~~~~~~
One can implement a F-CPU with different degrees of floating point operation
support or ``levels'', as the needs and the technologies dictate. The FP 
level 0 is the absence of \index{Floating Point}Floating Point hardware, and
the level increases as the hardware offers more features.

\begin{center}

\begin{tabular}{|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{~ Instruction {\htmlBackslash} Level ~
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{1
} & \multicolumn{1}{c| }{2
} & \multicolumn{1}{c| }{3
 } \\
 \hline
\multicolumn{1}{|r| }{fadd
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fsub
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fmul
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{int2f/f2int
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fiaprx, fsqrtiaprx
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fcmple, fcmpl
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fdiv, fsqrt
} & {
} & {
} & \multicolumn{1}{c| }{*
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{flog
} & {
} & {
} & {
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fexp
} & {
} & {
} & {
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{fmac
} & {
} & {
} & {
} & \multicolumn{1}{c| }{*
 } \\
 \hline
\multicolumn{1}{|r| }{faddsub
} & {
} & {
} & {
} & \multicolumn{1}{c| }{*
}
\\ \hline

\end{tabular}

\end{center}

~~~~~~
The FP level of a CPU should be read in the associated Special Register before
attempting to execute FP instructions.

\pagebreak


\section{Level 1 Floating Point Operations}

\input i7/Draft/Float/fadd
\input i7/Draft/Float/fsub
\input i7/Draft/Float/fmul
\input i7/Draft/Float/f2int
\input i7/Draft/Float/int2f
\input i7/Draft/Float/fiaprx
\input i7/Draft/Float/fsqrtiaprx
\input i7/Draft/Float/fcmple
\input i7/Draft/Float/fcmpl

\section{Level 2 Floating Point Operations}

\input i7/Draft/Float/fdiv
\input i7/Draft/Float/fsqrt


\section{Level 3 Floating Point Operations}

\input i7/Draft/Float/flog
\input i7/Draft/Float/fexp
\input i7/Draft/Float/fmac
\input i7/Draft/Float/faddsub



\chapter{Memory Access operations}


\section{Core Memory Access operations}

\input i7/Draft/Memory/load1
\input i7/Draft/Memory/store1


\section{Optional Memory Access operations}

\input i7/Draft/Memory/load2
\input i7/Draft/Memory/store2
\input i7/Draft/Memory/loadi
\input i7/Draft/Memory/storei
\input i7/Draft/Memory/loadf&storef
\input i7/Draft/Memory/cachemm



\chapter{Data move operations}

~~~~~~
These instructions typically do not use any Execution Unit.

\section{Core Data move operations}

\input i7/Draft/Memory/move
\input i7/Draft/Memory/loadcons
\input i7/Draft/SR/get
\input i7/Draft/SR/put


\section{Optional Data move operations}

\input i7/Draft/Memory/loadm
\input i7/Draft/Memory/storem

\input i7/Draft/SR/geti
\input i7/Draft/SR/puti


\chapter{Instruction Flow Control instructions}


\section{Core Instruction Flow Control instructions}

\input i7/Draft/Flow/nop
\input i7/Draft/Flow/jmp
\input i7/Draft/Flow/loadaddr
\input i7/Draft/Flow/loadaddri
\input i7/Draft/Flow/loopentry
\input i7/Draft/Flow/loop
\input i7/Draft/Flow/syscall
\input i7/Draft/Flow/halt
\input i7/Draft/Flow/rfe


\section{Optional Instruction Flow Control instructions}

\input i7/Draft/Flow/srbsave
\input i7/Draft/Flow/srbrestore
\input i7/Draft/Flow/serialize



