\subsection{\index{storem}storem}

\index{store multiple registers to memory}
STORE Multiple registers to memory


\begin{tabular}{l}
  {\bf storem r3, r2, r1}
\end{tabular}

~~~~~~
store registers starting from r3 to r2 from the location pointed in memory by r1.

~~~~~~
This instruction uses the SRB mechanism to store multiple contiguous
registers to memory. This can be used during function prologs where
the classical RISC approach stores one register at a time.

~~~~~~
The endianness of the operation is the endianness of the machine and the
registers are full-length because it uses the SRB machinery verbatim. It 
benefits from the SRB reordering mechanism so when a value is needed but 
is not yet loaded, the SRB modifies the loading order. The operation is 
also performed in the background with few overhead for the application. 
Unlike the natural use of the SRB, this instruction can raise exceptions 
like all load operation.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_STOREM
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}

~

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} L/S Unit\\
{\em Latency :} unknown\\
{\em Throughput :} unknown\\

~

\pagebreak

