\subsection{\index{store}store}

\index{adjust the endianess, store the result in memory and update the
pointer}
adjust the Endianness, STORE the result in memory and update the pointer


\begin{tabular}{l}
  {\bf store[e] r3, r2, r1} \\
\end{tabular}

~~~~~~
Performs mem[r2] = endian(e,r1)\\
~~~~~~~~~~~~r2 = r2 + r3.

~~~~~~
STORE adjusts the endianness of r1 according to the Endian flag and stores
the item of the defined size to memory, at the location pointed to by r2. 
This version uses the same opcode as the core version but differs by the r3
parameter which makes it a {\bf 3r1w} instruction. In addition to the core 
version, the r3 parameter is used to update the r2 pointer by adding them 
in parallel with the memory operation. Note that if r3 contains 0, the core 
version is executed : the CPU checks the zero flags, instead of checking 
the register number.

~~~~~~
This instruction can trigger two exceptions (in order of decreasing priority)
:

\begin{itemize}
\item {\bf Alignment fault} : One or more LSB of the pointer are set. The
number of significant LSB varies with the size flag. The F-CPU does not allow
unaligned memory accesses.

\item {\bf Page fault} : The location referenced by r2 is not mapped in the
internal TLB, and the OS kernel must update it, after checking for address 
range validity and access rights.

\end{itemize}

~~~~~~
The L/S Unit of the FC0 can perform the store operation with no latency for
the entire pipeline when there is a free line in the memory bufer. If there 
are too much pending memory access requests, the pipeline must wait at the 
decoding stage for a memory buffer line to be freed.

~~~~~~
The behaviour of the pointer update obeys to the simplest arithmetics rules.
No saturation is performed and the pointer will wrap around in memory.

~~~~~~
After the addition is performed, the result will be submitted to the DTLB
(Data virtual address Translation Lookaside Buffer) to check for the pointer
validity in advance. In the same time, the processor can check the sign of 
r3 in order to predict in which direction the pointer advances and prepare 
the memory buffer.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_STORE
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size Flag
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-e postfix
} & {0 : little endian
} & {Endian Flag
 } \\
\multicolumn{1}{|c| }{
} & {
} & {1 : big endian
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{20-18
} & {-0 .. -7 postfix
} & {000 .. 111
} & {Reserved for the Stream Hint bits
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Load/Store Unit and Add/Sub Unit.\\
{\em Latency :} 2 cycles if the item is already in the memory buffer,
undetermined (but more) otherwise. The pointer update takes three cycles 
(2 ASU + 1 DTLB).\\
{\em Throughput :} 1 operation per cycle per LSU (peak).\\

~

\pagebreak


