\subsection{\index{store}store}

\index{adjust the endianness and store the result in memory}
adjust the Endianness and STORE the result in memory


\begin{tabular}{l}
  {\bf store r2, r1} \\
  {\bf storee r2, r1} \\
\end{tabular}

~~~~~~
Performs mem[r2] = endian(e,r1).

~~~~~~
STORE adjusts the endianness of r1 according to the Endian flag and stores the
item of the defined size to memory, at the location pointed to by r2.

~~~~~~
This instruction can trigger two exceptions (in order of decreasing priority) :

\begin{itemize}
\item {\bf Alignment fault} : One or more LSB of the pointer are set. The 
number of significant LSB varies with the size flag. The F-CPU does not allow 
unaligned memory accesses.

\item {\bf Page fault} : The location referenced by r2 is not mapped in the 
internal TLB, and the OS kernel must update it, after checking for address 
range validity and access rights.

\end{itemize}

~~~~~~
The L/S Unit of the FC0 can perform the store operation with no latency for 
the entire pipeline when there is a free line in the memory bufer. If there 
are too much pending memory access requests, the pipeline must wait at the 
decoding stage for a memory buffer line to be freed.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 25
} & {24 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_STORE
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size Flag
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-e postfix
} & {0 : little endian
} & {Endian Flag
 } \\
\multicolumn{1}{|c| }{
} & {
} & {1 : big endian
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{20-18
} & {-0 .. -7 postfix
} & {000 .. 111
} & {Reserved for the Stream Hint bits
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Load/Store Unit\\
{\em Latency :} none if the memory buffer has a free slot, undetermined
(but more) otherwise.\\
{\em Throughput :} 1 operation per cycle per LSU (peak).\\

~

\pagebreak
