\subsection{\index{move}move}

conditionally MOVE a register into another
\index{conditionnally move a register into another}


\begin{tabular}{l}
  {\bf moves[z/m/l/nz/nm/nl] r3, r2, r1}\\
  {\bf move	r2, r1}
\end{tabular}

~~~~~~
IF (condition(r3)) then r1 = r2

~~~~~~
The value of r3 is checked with the specified condition. If the condition is 
right, r2 is copied to r3 according to the size parameter. The condition is 
tested on the full register, and only the move uses the size flag.

~~~~~~
Moving to r0 has no effect.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {0 ~ ~ ~ ~ ~ ~ ~ ~ 7
} & {8 ~ ~ ~ ~ ~ ~ 13
} & {14 ~ ~ ~ ~ ~ ~ 19
} & {20 ~ ~ ~ ~ ~ ~ 25
} & {26 ~ ~ ~ ~ ~ ~ 31
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_MOVE
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{8-9
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{10
} & {-n
} & {1 if negated
} & {Negation of the condition
 } \\
 \hline
\multicolumn{1}{|c| }{11-12
} & {-z, -m, -l, -nz, -nm, -nl postfix
} & {(see below)
} & {Condition
 } \\
 \hline
\multicolumn{1}{|c| }{13
} & {-s
} & {1 if sign-extended
} & {Sign-extension flag
}
\\ \hline

\end{tabular}

\begin{tabular}{|l|l|l|}
 \hline
\multicolumn{1}{|r| }{Value
} & \multicolumn{1}{c| }{Syntax
} & \multicolumn{1}{c| }{Meaning
}
\\ \hline
\multicolumn{1}{|c| }{000
} & {-z
} & {zero
}
\\ \hline
\multicolumn{1}{|c| }{001
} & {
} & {unassigned
}
\\ \hline
\multicolumn{1}{|c| }{010
} & {-m
} & {msb == 1
}
\\ \hline
\multicolumn{1}{|c| }{011
} & {-l
} & {lsb == 0
}
\\ \hline
\multicolumn{1}{|c| }{100
} & {-nz
} & {not zero
}
\\ \hline
\multicolumn{1}{|c| }{101
} & {
} & {unassigned
}
\\ \hline
\multicolumn{1}{|c| }{110
} & {-nm
} & {msb == 0
}
\\ \hline
\multicolumn{1}{|c| }{111
} & {-nl
} & {lsb == 1
}
\\ \hline
\end{tabular}

~

{\bf Examples :}
\end{center}

{\bf r1} contains 0x0124356789ABCDEF\\
{\bf r2} contains 0xFEDCBA9876543210

{\tt {\bf move.b r1,r2} ; r2 = 0xFEDCBA98765432FE\\
{\bf if LSB r1 move.b r1,r2} ; r2 = 0xFEDCBA98765432FE\\
{\bf if MSB r1 move.b r1,r2} ; r2 = 0xFEDCBA9876543210 (do nothing)\\
{\bf if r1==0 move.b r1,r2} ; r2 = 0xFEDCBA9876543210 (do nothing)\\
}

~

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} none\\
{\em Latency :} 2 cycle (Xbar)\\
{\em Throughput :} 1 per cycle per instruction.\\
{\em Scheduling :}\\
\begin{center}

\begin{tabular}{|l|l|l|l|l|}
 \hline
{Cycle
} & { ~ ~ ~ ~ 1 ~ ~ ~ ~
} & { ~ ~ ~ ~ 2 ~ ~ ~ ~
} & { ~ ~ ~ ~ 3 ~ ~ ~ ~
} & { ~ ~ ~ ~ 4 ~ ~ ~ ~
 } \\
 \hline
\multicolumn{1}{|c| }{Stage ~ ~
} & \multicolumn{1}{c| }{Fetch
} & \multicolumn{1}{c| }{Decode/
} & \multicolumn{1}{c| }{[Xbar]
} & \multicolumn{1}{c| }{[Register
}
\\
\multicolumn{1}{|c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{Register Read
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{write]
}
\\ \hline

\end{tabular}

\end{center}


~

\pagebreak

