\subsection{\index{loadcons}loadcons}

\index{load a constant into a register}
LOAD a CONSTant into a register


\begin{tabular}{l}
  {\bf loadcons[p/s] Imm16, r1}
\end{tabular}

~~~~~~
if p is set :\\
r1 = (r1 {\htmlLt}{\htmlLt} 16) OR Imm16\\
\\
else\\
r1 = sign\_extend((s {\htmlLt}{\htmlLt} 17) OR Imm16)\\

~~~~~~
This instruction do a 16 bits left shift and insert at the lower part the 
Imm16. With this instruction you can put the constant you whant in any 
size. This instruction is used in groups with loadcons to create a large
constant in a register.\\
~\\
If Imm is unknow, the assembler must put a suit of fixed number of LOADCONS
to enable relocation capabilitie.\\
~\\
If Imm can't fit into 16 bits, the assembler must provide an optimised suit
of LOADCONS.\\

~~~~~~
The architecture should ensure that a burst of LOADCONS does not stall the 
CPU. It is pipelinable in the FC0 so that a 64-bit constant only takes four 
cycles to complete.

~~~~~~

\begin{center}

\begin{tabular}{|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{2
} & \multicolumn{1}{c| }{16
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ 22
} & {21 ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_LOADCONSP
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Imm16
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}

\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23
} & {-p suffix
} & {1 if set
} & {load least significant 16 bits of the register; S is ignored
 } \\
 \hline
\multicolumn{1}{|c| }{22
} & {-s suffix
} & {1 if negated
} & {load full register; S is the sign bit
 } \\
 \hline
\end{tabular}

~

{\bf Examples :}
\end{center}

{\bf r1} contains 0x0124356789ABCDEF, the following instructions load
0xFEDCBA9876543210

{\tt
{\bf loadcons.0 0x3210, r1 } ; r1 = 0x0123456789AB3210\\
{\bf loadcons.1 0x7654, r1 } ; r1 = 0x0123456776543210\\
{\bf loadcons.2 0xBA98, r1 } ; r1 = 0x0123BA9876543210\\
{\bf loadcons.3 0xFEDC, r1 } ; r1 = 0xFEDCBA9876543210\\
}

~

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} none\\
{\em Latency :} 1 cycle (Xbar)\\
{\em Throughput :} 1 per cycle per instruction.\\
{\em Scheduling :}\\
\begin{center}

\begin{tabular}{|l|l|l|l|l|}
 \hline
{Cycle
} & { ~ ~ ~ ~ 1 ~ ~ ~ ~
} & { ~ ~ ~ ~ 2 ~ ~ ~ ~
} & { ~ ~ ~ ~ 3 ~ ~ ~ ~
} & { ~ ~ ~ ~ 4 ~ ~ ~ ~
 } \\
 \hline
\multicolumn{1}{|c| }{Stage ~ ~
} & \multicolumn{1}{c| }{Fetch
} & \multicolumn{1}{c| }{Decode/\htmlBR
Register Read
} & \multicolumn{1}{c| }{Xbar
} & \multicolumn{1}{c| }{Register\htmlBR
write
}
\\ \hline

\end{tabular}

\end{center}

~

\pagebreak


