\subsection{\index{load}load}

\index{load a memory item into a register, adjust the endianness and update
the pointer}
LOAD a memory item into a register, adjust the Endianness and update the
pointer


\begin{tabular}{l}
  {\bf load r3, r2, r1} \\
  {\bf loade r3, r2, r1} \\
\end{tabular}

~~~~~~
Performs : r1 = endian(e,mem[r2])\\
~~~~~~~~~~~~r2 = r2 + r3

~~~~~~
LOAD fetches the memory item pointed to by r2, changes the
endianness according to the endian flag, puts the result of the specified
size into r1. This version uses the same opcode as the core version but
differs by the r3 parameter which makes it a {\bf 2r2w} instruction. In 
addition to the core version, the r3 parameter is used to update the r2 
pointer by adding them in parallel with the memory operation. Note that if 
r3 contains 0, the core version is executed : the CPU checks the zero flags, 
instead of checking the register number.

~~~~~~
This instruction can trigger two exceptions (in order of decreasing priority):

\begin{itemize}
\item {\bf Alignment fault} : One or more LSB of the pointer are set. The
number of significant LSB varies with the size flag. The F-CPU does not 
allow unaligned memory accesses.

\item {\bf Page fault} : The location referenced by r2 is not mapped in the
internal TLB, and the OS kernel must update it, after checking for address 
range validity and access rights.

\end{itemize}

{\bf Prefetch} :\\
~~~~~~
In the case where the destination register is r0 (the NULL register), none of 
these exceptions are raised. This instruction form serves as a {\bf prefetch} 
instruction that is issued several cycles before the actual reference is 
performed. The prefetch form prepares the memory hierarchy, the protection 
mechanisms and all the internal hidden flags for an eventual exception. The 
CPU can use the time between the prefetch and the actual fetch to prepare the 
page fault handler and the memory hierarchy so that the actual fetch will have 
almost no latency, whenever there is a fault or not.

~~~~~~
The behaviour of the pointer update obeys to the simplest arithmetics rules.
No saturation is performed and the pointer will wrap around in memory.

~~~~~~
After the addition is performed, the result will be submitted to the DTLB
(Data virtual address Translation Lookaside Buffer) to check for the pointer
validity in advance. As soon as the physical address is known, the processor 
can also prefetch the data if necessary, issuing a fetch command to the cache
or the external memory. In the same time, the processor can check the sign of
r3 in order to predict in which direction the pointer advances and prepare 
the memory buffer.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_LOAD
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size Flag
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-e postfix
} & {0 : little endian
} & {Endian Flag
 } \\
\multicolumn{1}{|c| }{
} & {
} & {1 : big endian
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{20-18
} & {-0 .. -7 postfix
} & {000 .. 111
} & {Reserved for the Stream Hint bits
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Load/Store Unit and Add/Sub Unit.\\
{\em Latency :} 2 cycles if the item is already in the memory buffer, 
undetermined (but more) otherwise. The pointer update takes three cycles 
(2 ASU + 1 DTLB).\\
{\em Throughput :} 1 operation per cycle per LSU (peak).\\

~

\pagebreak


