\subsection{\index{load}load}

\index{load a memory item into a register and adjust the endianness}
LOAD a memory item into a register and adjust the Endianness


\begin{tabular}{l}
  {\bf load r2, r1} \\
  {\bf loade r2, r1} \\
\end{tabular}

~~~~~~
Performs r1 = endian(e,mem[r2]).

~~~~~~
LOAD fetches the memory item pointed to by r2, changes the endianness according 
to the endian flag, and puts the result of the specified size into r1.

~~~~~~
This instruction can trigger two exceptions (in order of decreasing priority) :

\begin{itemize}
\item {\bf Alignment fault} : One or more LSB of the pointer are set. The 
number of significant LSB varies with the size flag. The F-CPU does not allow 
unaligned memory accesses.
\item {\bf Page fault} : The location referenced by r2 is not mapped in the
internal TLB, and the OS kernel must update it, after checking for address 
range validity and access rights.
\end{itemize}

{\bf Prefetch} :\\
~~~~~~
In the case where the destination register is r0 (the NULL register), none of
these exceptions are raised. This instruction form serves as a {\bf prefetch}
instruction that is issued several cycles before the actual reference is 
performed. The prefetch form prepares the memory hierarchy, the protection 
mechanisms and all the internal hidden flags for an eventual exception. The 
CPU can use the time between the prefetch and the actual fetch to prepare the 
page fault handler and the memory hierarchy so that the actual fetch will have 
almost no latency, whenever there is a fault or not.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_LOAD
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size Flag
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-e postfix
} & {0 : little endian
} & {Endian Flag
 } \\
\multicolumn{1}{|c| }{
} & {
} & {1 : big endian
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{20-18
} & {-0 .. -7 postfix
} & {000 .. 111
} & {Reserved for the Stream Hint bits
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Load/Store Unit\\
{\em Latency :} 2 cycles if the item is already in the memory buffer,
undetermined (but more) otherwise.\\
{\em Throughput :} 1 operation per cycle per LSU (peak).\\

~

\pagebreak

