\subsection{\index{cachemm}cachemm}

\index{cache memory management}
CACHE Memory Management


\begin{tabular}{l}
  {\bf cachemm r2, r1}
\end{tabular}

~~~~~~
Controls where a block of data or instructions is cached in the memory 
hierarchy. The block begins at the location pointed to by r2 and the size 
of the block is determined by r1.

~~~~~~
This instruction should provide an universal way to control the caching 
mechanism of the FCPU accross all the variants that may appear. The 
instruction may operate on a page or cache line granularity, in an 
implementation dependent way. This instruction is purely a hint for the CPU 
that may or may not transfer data between different memory levels (that 
physically exist or not).

~~~~~~
The instruction can act in either of these two directions :\\
- Flush : all the data present in the levels between the CPU and the parameter
are flushed to at most this level. No data in the defined block is left in the 
above levels.\\
- Prefetch : loads the data belonging to the block in at least the level
defined as parameter.

~~~~~~
In addition, the L flag is used to influence the LRU tags in order to define
the importance and the use of the block. L means Lock'' and its absence 
unlocks the data from the level.

~~~~~~
The C flag, when supported, tries to compress the block when it is flushed, or
decompress it when it is loaded, with a dedicated hardware.

~~~~~~
The status of this instruction could be read from a Special Register.
This instruction is very important for memory management, and should be used
when performing SMC or DMA for memory coherency. The OS can also lock the main 
TLB tables and the critical codes so that TLB replacement doesn't thrash the 
cache.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{4
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ ~ ~ 16
} & {15 ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_CACHEMM
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}


\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size Flag
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-f postfix
} & {0 : Flush
} & {Direction flag
 } \\
\multicolumn{1}{|c| }{
} & {-p postfix
} & {1 : Prefetch
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {
} & {[l]
} & {Lock. The data will be used a lot
 } \\
 \hline
\multicolumn{1}{|c| }{19
} & {
} & {[c]
} & {De/Compress data on the fly
 } \\
 \hline
\multicolumn{1}{|c| }{18-16
} & {
} & {[0-7]
} & {Memory level (see table below)
}
\\ \hline

\end{tabular}

\begin{tabular}{|l|l|l|}
 \hline
\multicolumn{1}{|c| }{D} & \multicolumn{1}{c| }{000} & {onchip Data L1 cache
 } \\
 \hline
\multicolumn{1}{|c| }{I} & \multicolumn{1}{c| }{001} & {onchip Instructions L1
cache
 } \\
 \hline
\multicolumn{1}{|c| }{C} & \multicolumn{1}{c| }{010} & {onchip unified Cache
 } \\
 \hline
\multicolumn{1}{|c| }{ } & \multicolumn{1}{c| }{011} & {[unused]
 } \\
 \hline
\multicolumn{1}{|c| }{U} & \multicolumn{1}{c| }{100} & {offchip Unified cache
 } \\
 \hline
\multicolumn{1}{|c| }{L} & \multicolumn{1}{c| }{101} & {offchip Local memory
 } \\
 \hline
\multicolumn{1}{|c| }{G} & \multicolumn{1}{c| }{110} & {offchip Global memory
 } \\
 \hline
\multicolumn{1}{|c| }{V} & \multicolumn{1}{c| }{111} & {Virtual memory (hard
disk)
}
\\ \hline

\end{tabular}

~

{\bf Examples :}
\end{center}

~~~~~~
{\tt {\bf cachemmfg ra,rb}} flushes rb bytes starting at address ra
from every memory level until global memory. Any cache
(L1, L2, local...) containing data that belong to the block
is updated in main memory and the corresponding cache spaces are
freed (available for future use). this should be executed everytime
the programer knows that he won't use a block of data until a certain
moment, and the cache level is a hint for performance.

~~~~~~
{\tt {\bf cachemmpu ra,rb}} copies the data block at address ra and size rb
that is present in lower memory levels (virtual, global, local)
to the unified offchip memory (at least'', which means that some parts
may be present closer to the processor).

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Load/Store Unit (?).\\
{\em Latency :} unknown, context dependent.\\
{\em Throughput :} one instruction at a time. And it's slow.\\

~

\pagebreak

