\subsection{\index{mul}mul}

\index{multiplication}
MULtiplication

\begin{tabular}{l}
  {\bf mul[h][s] r3, r2, r1} \\
  {\bf smul[h][s] r3, r2, r1} \\
\end{tabular}


~~~~~~
Computes r1 = r2 x r3

~~~~~~
{\bf mul} performs an integer multiplication of the two source
operands (r3 x r2) and puts the result in the destination operand
(r1). The size flags indicate the size of the source operands.


\begin{itemize}
\item The {\bf size }flag indicates that {\bf mul }performs the
multiplication on the whole operands or only on a part of the
operands. It only puts the lower part of the result in the destination.

\item The {\bf SIMD }flag indicates that {\bf mul }performs
multiple multiplications on parts of the operand (the size of these
parts is defined by the {\bf size }flags).

\item The {\bf sign }flag indicates that {\bf mul }will consider
the operands as signed by extending the MSB.

\item The {\bf high }flag indicates that {\bf mul }will also stores
the higher part of the result in r1\^1. It works in a similar fashion to
the carry flag of the addition.
\end{itemize}

~~~~~~
{ \em Remark :} the multiplication computation is slow and heavy, try to use
powers-of-two multipliers as to simply shift the source operand, which takes 
only a cycle to perform in the FC0.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_MUL
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {(none yet)
} & {0
} & {Reserved
 } \\
 \hline
\multicolumn{1}{|c| }{19
} & {-s postfix
} & {1 if set
} & {Sign flag
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {-h postfix
} & {1 if set
} & {High flag ( {\bf 2r2w} )
}
\\ \hline

\end{tabular}


~

{\bf Examples : }
\end{center}


{\em Scalar :}

R1 contains 0x23 (we only consider the lower byte in the registers)\\
R2 contains 0x36

{\tt
{\bf mul.b r1,r2,r3 }: r3 = 0x62 (default)\\
{\bf mulh.b r1,r2,r3 }: r3 = 0x62 , r4 = 0x07 (High flag)\\
}

{\em SIMD :}

R1 contains 0x00 00 00 00 00 00 00 00 (in a 64-bit system)\\
R2 contains 0x00 00 00 00 00 00 00 00

{\tt
{\bf smul.b r1,r2,r3 }: r3 = 0x00 00 00 00 00 00 00 00 \\
{\bf smulh.b r1,r2,r3 }: r3 = 0x00 00 00 00 00 00 00 00 , r4 = 0x00 00 00 00
00 00 00 00\\
}
[Completed later, when all the errors will be corrected]

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Integer Multiply Unit\\
{\em Latency :} unknown ATM, depends on the size of the operands.\\
{\em Throughput :} unknown ATM, probably 1 operation per cycle per IMU
(pipelined multiplier).\\
{\em Scheduling :}\\
\begin{center}

\begin{tabular}{|c|c|c|c|c|c|c|}
 \hline
{Cycle
} & { 1
} & { 2
} & { 3
} & { ?
} & { +1
} & { +2
 } \\
 \hline
\multicolumn{1}{|c| }{Stage ~ ~
} & \multicolumn{1}{c| }{Fetch
} & \multicolumn{1}{c| }{Decode/
} & \multicolumn{1}{c| }{Xbar
} & \multicolumn{1}{c| }{IMU(?)
} & \multicolumn{1}{c| }{Xbar
} & \multicolumn{1}{c| }{Register
}
\\
\multicolumn{1}{|c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{Register Read
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{write
}
\\ \hline

 \end{tabular}
\end{center}

\pagebreak

