\subsection{\index{mac}mac}

\index{multiply and accumulate}
Multiply and ACcumulate


\begin{tabular}{l}
  {\bf mac[l/h][s] r3, r2, r1} \\
  {\bf smac[l/h][s] r3, r2, r1} \\
\end{tabular}


~~~~~~
Computes r1 = r1 + ( r2 x r3 )

~~~~~~
{\bf mac} performs an integer multiplication of the two source
operands (r3 x r2) and adds the result to the destination operand (r1).
The size flags indicate the size of the source operands, the granularity''
of the destination operand is twice this size if the hardware can do it.


\begin{itemize}
\item The {\bf size }flag indicates that {\bf mac }performs the
operation on the whole operands or only on a part of the operands.

\item The {\bf SIMD }flag indicates that {\bf mac }performs
multiple operations on parts of the operand (the size of these
parts is defined by the {\bf size }flags).

\item The {\bf sign }flag indicates that {\bf mac }will consider
the operands as signed by extending the MSB.

\item The {\bf high }flag indicates that {\bf mac }will only operate
on the high halfes of the operands (in SIMD mode).

\end{itemize}

~~~~~~
{ \em Remark :} This instruction is mostly used in computation kernels that
involve some kind of convolution or frequency analysis. It will be extended 
later as the needs get clearer. The behaviour of the accumulation when the 
data overflow is still undefined so calibrate the input values so that the 
dynamic range is not exceeded in the computation loop. There is no sticky
saturation'' either.

~~~~~~
{ \em Remark 2 :} this instruction reads three operands and therefore is a
{\bf 3r1w} operation that is not in the core. Its implementation depends on
architectural parameters.
\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_MAC
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {(none yet)
} & {0
} & {Reserved
 } \\
 \hline
\multicolumn{1}{|c| }{19
} & {-s postfix
} & {1 if set
} & {Sign flag
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {-h postfix
} & {1 if set
} & {High flag
}
\\ \hline

\end{tabular}


~

{\bf Example : }
\end{center}


{\em Scalar :}

R1 contains 0x23 (we only consider the lower byte in the registers)\\
R2 contains 0x36\\
R3 contains 0x0136

{\tt
{\bf mac.b r1,r2,r3 }: r3 = 0x0868\\
}

[To be completed later, when all the other errors will be corrected]

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Integer Multiply Unit then Add/Sub Unit\\
{\em Latency :} unknown ATM, depends on the size of the operands.\\
{\em Throughput :} unknown ATM, probably 1 operation per cycle per IMU+ASU
(pipelined multiplier and adder).\\

~

\pagebreak


