\subsection{\index{div}div}

\index{division}
DIVision


\begin{tabular}{l}
  {\bf div[r][s] r3, r2, r1} \\
  {\bf sdiv[r][s] r3, r2, r1} \\
\end{tabular}

~~~~~~
Computes r1 = r2 / r3

~~~~~~
{\bf div }performs an integer division of the two source operands
(r3 / r2) and puts the result in destination operand (r1). The size defined by
the size flags corresponds to the size of the source operands.

\begin{itemize}
\item The {\bf size }flag indicates that {\bf div }performs the
division on the whole operands or only on a part of the operands.

\item The {\bf SIMD }flag indicates that {\bf div }performs
multiple division on parts of the operand (the size of these parts
is defined by the {\bf size }flags).

\item The {\bf Sign }flag determines if the operands should be treated
as unsigned or signed values.

\item The {\bf Remainder }flag specifies that the remainder of the division
is written to the register (r1\^1).

\end{itemize}

~~~~~~
This instruction triggers a math fault if the Reg2 operand is cleared (=0).
This behaviour could be avoided with saturated arithmetics.

~~~~~~
{\em Remark :} the division computation is slow and heavy, try to use
powers-of-two divisors as to simply shift the source operand, which takes
only a cycle to perform in the FC0.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_DIV
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {-r postfix (or -rem postfix)
} & {1 if set
} & {Remainder flag ( {\bf 2r2w} )
}
\\ \hline
\multicolumn{1}{|c| }{19
} & {-s postfix
} & {1 if set
} & {Sign flag
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {(none yet)
} & {0
} & {Reserved
 } \\
 \hline

\end{tabular}


~

{\bf Examples : }
\end{center}


{\em Scalar :}

R1 contains 0x10 (we only consider the lower byte in the registers)\\
R2 contains 0x05

{\tt
{\bf div.b r1,r2,r3 }: r3 = 0x03\\
{\bf divr.b r1,r2,r3 }: r3 = 0x03 , r4 = 0x01\\
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Integer Divide Unit\\
{\em Latency :} unknown ATM, depends on the size of the operands.\\
{\em Throughput :} unknown ATM, probably equal to the latency (not
pipelined).\\
{\em Scheduling :}\\
\begin{center}

\begin{tabular}{|c|c|c|c|c|c|c|}
 \hline
{Cycle
} & { 1
} & { 2
} & { 3
} & { ?
} & { +1
} & { +2
} \\
 \hline
\multicolumn{1}{|c| }{Stage ~ ~
} & \multicolumn{1}{c| }{Fetch
} & \multicolumn{1}{c| }{Decode/
} & \multicolumn{1}{c| }{Xbar
} & \multicolumn{1}{c| }{IDU(?)
} & \multicolumn{1}{c| }{Xbar
} & \multicolumn{1}{c| }{Register
}
\\
\multicolumn{1}{|c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{Register Read
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{
} & \multicolumn{1}{c| }{write
}
\\ \hline

\end{tabular}

\end{center}

\pagebreak


