\subsection{\index{addsub}addsub}

\index{addition and substraction}
ADDition and SUBstraction


\begin{tabular}{l}
 {\bf addsub[s] r3, r2, r1} \\
 {\bf saddsub[s] r3, r2, r1} \\
\end{tabular}

~~~~~~
Computes r1 = r2 + r3 and r1\^1 = r2 - r3


\begin{itemize}
\item The {\bf size }flag indicates that it performs the
operation on the whole operands or only on a part of the operands.

\item The {\bf SIMD }flag indicates that it performs
multiple operations on parts of the operand (the size of these
parts is defined by the {\bf size }flags).
\end{itemize}

~~~~~~
{ \em Remark :} This instruction is mostly used in computation kernels like
FFT. It is included in the F-CPU because it allows the {\bf 2r2w} operation forms.
Its implementation depends on architectural parameters, like the possibility
to perform both addition and substraction at the same time.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_ADDSUB
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {(none yet)
} & {0
} & {Reserved
 }\\
 \hline
\multicolumn{1}{|c| }{19
} & {-s suffix
} & {1 if set
} & {Saturation flag
 }\\
 \hline
\multicolumn{1}{|c| }{18
} & {(none yet)
} & {0
} & {Reserved
}
\\ \hline

\end{tabular}


~
{\bf Example : }
\end{center}


R1 contains 0x23 (we only consider the lower byte in the registers)\\
R2 contains 0x36

{\tt
{\bf addsub.b r1,r2,r3 }: r3 = 0x59 , r4 = 0xED\\
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Add/Sub Unit\\
{\em Latency :} 1 cycle for 8-bit data, 2 cycles for 16-bit to 64-bit data\\
{\em Throughput :} 1 operation per cycle per ASU.\\

~

\pagebreak


