\subsection{\index{add}add}

\index{addition}
ADDition

\begin{tabular}{l}
 {\bf add[c/s] r3, r2, r1} \\
 {\bf adds r3, r2, r1} \\
 {\bf addc r3, r2, r1} \\
 {\bf sadd[c/s] r3, r2, r1} \\
 {\bf sadds r3, r2, r1} \\
 {\bf saddc r3, r2, r1} \\
\end{tabular}


~~~~~~
Computes r1 = r2 + r3

~~~~~~
{\bf add }performs an integer addition of the two source operands
(r3 + r2) and puts the result in the destination operand (r1).


\begin{itemize}
\item The {\bf size }flag indicates that {\bf add }performs the
addition on the whole operands or only on a part of the operands.

\item The {\bf SIMD }flag indicates that {\bf add }performs
multiple addition on parts of the operand (the size of these parts
is defined by the {\bf size }flags).

\item The {\bf saturate }flag indicates that {\bf add }does not
wrap'' if the result is bigger than the size of the operands.

\item The {\bf carry }flag indicates that the eventual carry
value is written to register number (r1\^1). If no carry has been generated,
the neighbour register is cleared (0x00), otherwise the LSB has been set
(0x01).
\end{itemize}


\begin{center}

\begin{tabular}{|c|c|c|c|c|c|}
 \hline
 \multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} \\
 \hline
\multicolumn{1}{|c| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|c| }{function :
} & \multicolumn{1}{c| }{OP\_ADD
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\
 \hline

\end{tabular}



\begin{tabular}{|c|c|c|c|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {*
} & {Defines the size parameter
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {s- prefix
} & {1 if set
} & {Defines if the operation is SIMD
 } \\
 \hline
\multicolumn{1}{|c| }{20
} & {(none yet)
} & {0
} & {Reserved
 } \\
 \hline
\multicolumn{1}{|c| }{19
} & {-s postfix
} & {1 if set
} & {Saturation flag
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {-c postfix
} & {1 if set
} & {Carry flag ( {\bf 2r2w} )
}
\\ \hline

\end{tabular}


~

{\bf Examples : }
\end{center}


{\em Scalar :}

R1 contains 0xF8 (we only consider the lower byte in the registers)\\
R2 contains 0x0F

{\tt
{\bf add.b r1,r2,r3 }: r3 = 0x07 (default behaviour)\\
{\bf adds.b r1,r2,r3 }: r3 = 0xFF (saturation)\\
{\bf addc.b r1,r2,r3 }: r3 = 0x07, r4= 0x01 (carry)\\
}

{\em SIMD :}

R1 contains 0x000000F800000001 (in a 64-bit system)\\
R2 contains 0x0000000F00000002

{\tt
{\bf sadd.b r1,r2,r3 }: r3 = 0x0000000700000003 (default behaviour)\\
{\bf sadds.b r1,r2,r3 }: r3 = 0x000000FF00000003 (saturation)\\
{\bf saddc.b r1,r2,r3 }: r3 = 0x0000000700000003 , r4= 0x0000000100000000
(carry)
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Add/Sub Unit\\
{\em Latency :} 1 cycle for 8-bit data, 2 cycles for 16-bit to 64-bit
data\\
{\em Throughput :} 1 operation per cycle per ASU.\\
{\em Scheduling :}\\
\begin{center}
byte chunks :

\begin{tabular}{|c|c|c|c|c|c|c|}
 \hline
{Cycle
} & { 1
} & { 2
} & { 3
} & { 4
} & { 5
} & { 6
 } \\
 \hline
\multicolumn{1}{|l| }{Stage ~ ~
} & \multicolumn{1}{l| }{Fetch
} & \multicolumn{1}{l| }{Decode/
} & \multicolumn{1}{l| }{Xbar
} & \multicolumn{1}{l| }{ASU(1)
} & \multicolumn{1}{l| }{Xbar
} & \multicolumn{1}{l| }{Register
}
\\
\multicolumn{1}{|l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{Register Read
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{write
}
\\  \hline
\end{tabular}

word chunks :

\begin{tabular}{|c|c|c|c|c|c|c|c|}
 \hline
{Cycle
} & { 1
} & { 2
} & { 3
} & { 4
} & { 5
} & { 6
} & { 7
 } \\
 \hline
\multicolumn{1}{|l| }{Stage ~ ~
} & \multicolumn{1}{l| }{Fetch
} & \multicolumn{1}{l| }{Decode/
} & \multicolumn{1}{l| }{Xbar
} & \multicolumn{1}{l| }{ASU(1)
} & \multicolumn{1}{l| }{ASU(2)
} & \multicolumn{1}{l| }{Xbar
} & \multicolumn{1}{l| }{Register
}
\\
\multicolumn{1}{|l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{Register Read
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{
} & \multicolumn{1}{l| }{write
}
\\ \hline

\end{tabular}

\end{center}


\pagebreak

