\subsection{\index{loopentry}loopentry}

\index{loop entry point}
LOOP ENTRY point


\begin{tabular}{l}
  {\bf loopentry r1}
\end{tabular}

~~~~~~
r1 = PC + 4 then check the result in the ITLB.

~~~~~~
This instruction copies the address of the next instruction in r1 as to mark 
the entry point of a loop. A jmpa instruction will then use r1 instead of 
recalculating a relative offset at each loop iteration.

~~~~~~
This instruction is a special case of the LOADADDR instruction with no D flag 
and no offset (r2 = 0).

~~~~~~
The Size flag is not used, all registers are used in full length.

\begin{center}

\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{18
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_LOADADDR
} & \multicolumn{1}{c| }{0
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} none (theoretically)\\
{\em Latency :} none.\\
{\em Throughput :} 1 per cycle.\\

~

\pagebreak
