\subsection{\index{loadaddri}loadaddri}

\index{load a relative address to a register with an immediate offset}
LOAD a relative ADDRess to a register with an Immediate offset


\begin{tabular}{l}
  {\bf loadaddri[d] Imm16, r1} \\
\end{tabular}

~~~~~~
r1 = PC + 4 + Imm16, check the result in the D/I TLB and eventually prefetch
the data.

~~~~~~
If the {\bf D}ata flag is set (1), the Data TLB is used instead of the
Instruction TLB to check the pointer validity and the register is associated'' 
to either the L/S Unit or the Fetcher unit on success. Eventually, the CPU 
can prefetch the pointed data or prefetch the TLB miss code.

~~~~~~
This instruction is similar to loadaddr but uses an immediate offset. The {\bf
S} flag sign-extends the Imm16 data.

~~~~~~
The Size flag is not used, all registers are used in full length.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{1
} & \multicolumn{1}{c| }{1
} & \multicolumn{1}{c| }{16
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23
} & {22
} & {21 ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_LOADADDRI
} & \multicolumn{1}{c| }{D
} & \multicolumn{1}{c| }{S
} & \multicolumn{1}{c| }{Imm16
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} Add/Sub Unit\\
{\em Latency :} 2 cycles.\\
{\em Throughput :} 1 per cycle.\\

~

\pagebreak

