\subsection{\index{jmp}jmp}

\index{jump}
\index{conditional jump}
JuMP


\begin{tabular}{l}
  {\bf jmp[z/m/l/nz/nm/nl] r3, r2 [, r1]}\\
  {\bf jmp r2[, r1]}
\end{tabular}

~~~~~~
IF (condition(r3)) THEN
~~~~~~~~~~~~
r1 = PC + 4\\
~~~~~~~~~~~~
PC = r2

~~~~~~
If no condition are specified, the jump will always be done. If the condition is 
verified for r3, the content of the Program Counter is saved 

~~~~~~
If the condition is verified for r3, the content of the Program Counter is
saved to r1 and branches to the address pointed by r2. This instruction works
like a mix between MOVE and LOAD.

~~~~~~
If r1 is not cleared (written to register \#0 which is hardwired to 0) the
instruction is assimilated to a function call. The user is responsible of the 
stack frame''. Otherwise (r1=0) the value of PC is lost and the instruction is 
a normal jump.

~~~~~~
For several reasons, it is highly recommended that the destination of the jump 
is already associated to the register that contains the address, for example 
through a loadaddr instruction or by preserving r1 (overwriting it would cancel 
the association, for example when the stack'' in the register set is flushed 
then loaded from memory). When association'' is not certain or too early, it 
is recommended to prefetch the destination location a few tens of cycles in 
advance, otherwise it will result in a processor stall.

~~~~~~
The Size flag is not used, all registers are used in full length.

~~~~~~
This instruction can trigger two exceptions (in order of decreasing priority) :

\begin{itemize}

\item {\bf Alignment fault} : One or 2 LSB of r2 are set, the address is not
4-byte aligned. The F-CPU does not allow unaligned memory instructions.

\item {\bf Page fault} : The location referenced by r2 is not mapped in the
internal ITLB, and the OS kernel must update it, after checking for address 
range validity and access rights.

\end{itemize}

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_JMPA
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}


\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {
} & {0
} & {[undefined] branch probability hint
 } \\
 \hline
\multicolumn{1}{|c| }{21
} & {-n postfix
} & {1 if negated
} & {Negation of the condition
 } \\
 \hline
\multicolumn{1}{|c| }{20-19
} & {-z, -m, -l, -nz, -nm, -nl postfix
} & {(see below)
} & {Condition
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {
} & {0
} & {(reserved)
}
\\ \hline

\end{tabular}

~
\begin{tabular}{|l|l|l|}
 \hline
\multicolumn{1}{|r| }{Value
} & \multicolumn{1}{c| }{Syntax
} & \multicolumn{1}{c| }{Meaning
}
\\ \hline
\multicolumn{1}{|c| }{000
} & {-z
} & {zero
}
\\ \hline
\multicolumn{1}{|c| }{001
} & {
} & {unassigned
}
\\ \hline
\multicolumn{1}{|c| }{010
} & {-m
} & {msb == 1
}
\\ \hline
\multicolumn{1}{|c| }{011
} & {-l
} & {lsb == 0
}
\\ \hline
\multicolumn{1}{|c| }{100
} & {-nz
} & {not zero
}
\\ \hline
\multicolumn{1}{|c| }{101
} & {
} & {unassigned
}
\\ \hline
\multicolumn{1}{|c| }{110
} & {-nm
} & {msb == 0
}
\\ \hline
\multicolumn{1}{|c| }{111
} & {-nl
} & {lsb == 1
}
\\ \hline
\end{tabular}

~

{\bf Performance (FC0 only) :}
\end{center}

{\em Execution Unit :} none\\
{\em Latency :} 1 or 2 cycles if the destination is already in the
memory buffer, undetermined (but much more) otherwise.\\
{\em Throughput :} unknown ATM.\\

~

\pagebreak


