\subsection{\index{expand}expand}

EXPAND


\begin{tabular}{l}
  {\bf expandl r3, r2, r1} \\
  {\bf expandh r3, r2, r1} \\
\end{tabular}

~~~~~~
Mix chunks of r3 and r2 and puts the result into two halves of r1.

\begin{figure}[H]
  \begin{center}
    \includegraphics[width=15cm,draft=false]{expand.ps}
    \caption{Description of the expand instruction}
  \end{center}
\end{figure}

~~~~~~
This is the reverse operation of the {\bf mix} instruction. 
Depending on the {\bf h} flag, the lower or higher part of r3 and r2 are 
interleaved. The size of the source chunks is determined by the size flags.

\begin{center}

\begin{tabular}{|l|l|l|l|l|l|}
 \hline
\multicolumn{1}{|r| }{size :
} & \multicolumn{1}{c| }{8
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
} & \multicolumn{1}{c| }{6
 } \\
 \hline
\multicolumn{1}{|r| }{bits :
} & {31 ~ ~ ~ ~ ~ ~ ~ ~ 24
} & {23 ~ ~ ~ ~ ~ ~ 18
} & {17 ~ ~ ~ ~ ~ ~ 12
} & {11 ~ ~ ~ ~ ~ ~ 6
} & {5 ~ ~ ~ ~ ~ ~ 0
 } \\
 \hline
\multicolumn{1}{|r| }{function :
} & \multicolumn{1}{c| }{OP\_EXPAND
} & \multicolumn{1}{c| }{Flags
} & \multicolumn{1}{c| }{Reg 3
} & \multicolumn{1}{c| }{Reg 2
} & \multicolumn{1}{c| }{Reg 1
}
\\ \hline

\end{tabular}



\begin{tabular}{|l|l|l|l|}
 \hline
\multicolumn{1}{|c| }{~ ~ Flags ~ ~
} & \multicolumn{1}{c| }{Syntax
} & {Values
} & {Function
 } \\
 \hline
\multicolumn{1}{|c| }{23-22
} & {.q, .d or .b postfix
} & {~
} & {Size flag
 } \\
 \hline
\multicolumn{1}{|c| }{21-20
} & {(none yet)
} & {0
} & {Reserved
 } \\
 \hline
\multicolumn{1}{|c| }{19
} & {-l or -h postfix
} & {0 for -l
} & {High flag
 } \\
\multicolumn{1}{|c| }{
} & {
} & {1 for -h
} & {
 } \\
 \hline
\multicolumn{1}{|c| }{18
} & {(none yet)
} & {0
} & {Reserved
}
\\ \hline

\end{tabular}


~

{\bf Examples : }
\end{center}


R1 contains 0x0001020304050607 (in a 64-bit system)\\
R2 contains 0x08090A0B0C0D0E0F

{\tt
{\bf expandl.b r1,r2,r3 }: r3 = 0x09010B030D050F07\\
{\bf expandh.b r1,r2,r4 }: r4 = 0x08000A020C040E06\\
}

\begin{center}
{\bf Performance (FC0 only) :}
\end{center}


{\em Execution Unit :} Bit Shuffling Unit\\
{\em Latency :} 1 cycle\\
{\em Throughput :} 1 per cycle per BSU.\\

~

\pagebreak


